1. Field of the Invention
The present invention relates generally to a waveform shaping circuit and more particularly to a waveform shaping circuit for use with a digital signal transmission apparatus of a digital communication system.
2. Description of the Prior Art
A prior art digital signal transmission apparatus of a digital communication system is generally constructed as shown in FIG. 1. Referring to FIG. 1, the digital signal from a signal source 1 is supplied through a waveform shaping circuit 2 to a modulator 3. The modulated signal from the modulator 3 is supplied through a transmission line 4 to a demodulator 5 which constructs a receiving side. Then, the demodulated signal from the demodulator 5 is supplied through a slicer 6 to an output terminal 7. In this case, in order to realize the high efficiency digital signal transmission, the inter symbol interference and interference between adjacent channels must be minimized. Since according to the Nyquist transmission system, the inter symbol interference can be theoretically minimized to zero upon discrimination time and also the power outside a desired frequency band can be suppressed, in order to realize such Nyquist transmission system, the waveform shaping circuit 2 in FIG. 1 is constructed by such a binary transversal filter as shown in FIG. 2. Since this binary transversal filter can be designed in a direct time region, it is expected that the circuit can be made high in precision.
Referring to FIG. 2, reference numeral 8 designates a data input terminal to which a digital data signal to be transmitted is applied. Reference numerals 9a, 9b, . . . 9h respectively designate flip-flop circuits which constitute a shift register 9 which is supplied with the digital data signal from the data input terminal 8. Further, reference numeral 10 designates a clock input terminal to which a clock signal having the frequency twice as high as a data transfer rate is applied. The clock signal applied to this clock signal input terminal 10 is supplied to the flip-flop circuits 9a, 9b, . . . 9h constituting the shift register 9 as a shift signal. Reference numerals 11a, 11b, . . . 11h respectively designate resistors which construct a weighting circuit. Reference numeral 12 designates an output terminal. When the binary transversal filter as shown in FIG. 2 is used in the waveform shaping circuit 2 of FIG. 1, a desired impulse response can be approximated by a staircase waveform and such staircase waveform is passed through a low-pass filter so as to be smoothed, thus the Nyquist transmission system being formed.
However, according to the binary transversal filter constructing such waveform shaping circuit 2, the shift register 9 supplied with the input data signal is operated at the clock signal having the frequency twice as high as the data transfer rate and the output signals from the respective flip-flop circuits 9a, 9b, . . . 9h which constitute the shift register 9 are weighted by the resistance values of the weighting resistors 11a, 11b, . . . 11h. Since this binary transversal filter uses the resistors 11a, 11b, . . . 11h as the weighting circuits, when it is intended to increase the accuracy in waveform-shaping, a fine adjusting circuit must be provided for each tap or stage of the shift register. Further, this binary transversal filter has a defect that it will be directly affected by the logical amplitude fluctuation of the output from the shift register 9.
To solve the problem, such a waveform shaping circuit is proposed that instead of the resistors 11a, 11b, . . . 11h constituting the weighting circuit, there are provided a ROM (read only memory) 13 and a D/A (digital-to-analog) converting circuit 14 as shown in FIG. 3. Referring to FIG. 3, 8 output terminals of the shift register 9 formed of 8 flip-flop circuits 9a, 9b, . . . 9h are respectively connected to address control terminals of the ROM 13 having the address control terminals, the number thereof being corresponding to the number of the output terminals. In this case, the ROM 13 prepares a predetermined table by which the weighting operation of 2.sup.8 =256 words (one word is formed of 8 bits) is carried out. Then, the ROM 13 generates a data corresponding to the input pattern to the ROM 13 as the 8-bit digital value. The 8-bit digital output signal from the ROM 13 is supplied to the D/A converting circuit 14 and also a clock signal from an input terminal 10 is supplied to the D/A converting circuit 14. The output side of this D/A converting circuit 14 is connected to an output terminal 12. Other circuit elements are formed the same as those of FIG. 2. In the example shown in FIG. 3, since the ROM 13 is used, the weighting of each tap of the shift register 9 is prepared as the table, the value corresponding to the input pattern of the data signal is generated as the digital value and this digital value is converted to the desired analog waveform by the D/A converting circuit 14, there is an advantage that it is possible to remove such the defect that the resistor is used as the weighting circuit.
However, in the example of the waveform shaping circuit shown in FIG. 3, when the number of the stages of the shift register 9 is increased, since the capacity of the ROM 13 has a limit, there is a disadvantage that the aforesaid waveform shaping circuit can not be realized.
Therefore, such a waveform shaping circuit is proposed as shown in FIG. 4. As FIG. 4 shows, the data signal applied to the data input terminal 8 is supplied to a plurality of shift registers, for example, two shift registers 9.sub.1 and 9.sub.2 each formed of a predetermined stage, for example, 4 stages of flip-flop circuits 9a, 9b, 9c and 9d and having predetermined stages. 4 output terminals of each of these two shift registers 9.sub.1 and 9.sub.2 are respectively connected to address control terminals of two weighting ROMs 13.sub.1 and 13.sub.2, the number of address control terminals of each of which is made corresponding to the number of the output terminals. A clock signal P1 having the frequency twice as high as the data transfer rate, which is applied to the clock input terminal 10, is supplied to a 1/2 frequency divider 15. A clock signal P2 having the frequency equal to the data transfer rate and generated at the output of the 1/2 frequency divider 15 is spplied to each of the flip-flop circuits 9a, 9b, 9c and 9d of the shift register 9.sub.1 as a shift signal. At the same time, this clock signal P2 is supplied through a .pi. phase shifter 16, which shifts the phase of the clock signal P2 by .pi., to the respective flip-flop circuits 9a, 9b, 9c and 9d forming the shift register 9.sub.2 as a shift signal. 8-bit output signals from the ROMs 13.sub.1 and 13.sub.2 are respectively supplied to D/A converting circuits 14.sub.1 and 14.sub.2 and the clock signal P1 from the clock input terminal 10 is supplied to these A/D converting circuits 14.sub.1 and 14.sub.2. Then, analog output signals from the D/A converting circuits 14.sub.1 and 14.sub.2 are added together and then fed to an output terminal 12. In this case, since the shift register 9.sub.1 is driven by using the clock signal P2 having the frequency equal to the data transfer rate and the shift register 9.sub.2 is driven by the clock signal which results from phase-shifting the clock signal P2 by .pi. by the .pi. phase shifter 16, the shift registers 9.sub.1 and 9.sub.2 are equivalently driven by the clock signal having the frequency twice as high as the data transfer rate. In this case, it is sufficient that the ROMs 13.sub.1 and 13.sub.2 may prepare a predetermined table by which the weighting of, for example, 2.sup.4 =16 words (one word is formed of 8 bits) is carried out. Accordingly, it is possible to use the ROMs 13.sub.1 and 13.sub.2 each having a small capacity.
However, since the example shown in FIG. 4 employs the phase shifter circuit 16, there is a fear that the waveform shaping will be affected by the phase error of the clock signal. Also, since the number of the D/A converting circuits 14.sub.1 and 14.sub.2 must be made corresponding to the number of the ROMs 13.sub.1 and 13.sub.2, there is a disadvantage that the circuit arrangement thereof becomes large in size by so much.